1. Field of the Invention
The present invention relates to a DMA transfer device in which a single bus master device executes two kinds of DMA transfers.
2. Description of the Prior Art
In accordance with recent improvement of the throughput of a personal computer, a demand for performing by means of software a process which is conventionally performed by means of hardware is increasing. For example, there is a case where an encoded stream is fetched into a personal computer and then processed by means of software, and a stream produced as a result of the process is supplied to a device such as a video decoder to be output as an image or sound. FIG. 7 shows a configuration example of the prior art. An encoded first stream which is input through stream inputting means 701 is stored into first stream storing means 702. In response to a transfer request from a processing unit 704, first DMA transfer executing means 703 then executes a DMA transfer of the first stream stored in the first stream storing means 702 to a main storage unit 705. The processing unit 704 reads out the first stream from the main storage unit 705, performs software decoding on the first stream to produce a second stream, and stores the second stream into the main storage unit 705. In response to a transfer request from the processing unit 704, thereafter, second DMA transfer executing means 707 executes a DMA transfer of the second stream stored in the main storage unit 705 to second stream storing means 706.
In the prior art, a bus master device (corresponding to the first DMA transfer executing means 703 and the second DMA transfer executing means 707) which is employed in a DMA transfer is used in both the transfer from the first stream storing means 702 to the main storage unit 705, and that from the main storage unit 705 to the second stream storing means 706.
In the case where the amount of data requested in the first DMA transfer is larger than that of data accumulated in the first stream storing means 702, the bus master device cannot start the first DMA transfer until data of an amount which is equal to the requested data amount in the DMA transfer are accumulated in the first stream storing means 702. Similarly, in the case where the amount of data requested in the second DMA transfer is larger than the free capacity of the second stream storing means 706, the bus master device cannot start the second DMA transfer until a free capacity which is equal to the requested data amount in the DMA transfer is ensured in the second stream storing means 706.
As a result, in the case where, when the processing unit 704 requests the first DMA transfer after the processing unit requests the second DMA transfer, the free capacity is not sufficient for starting the transfer to the second stream storing means 706, for example, the bus master device must wait to perform the first DMA transfer until the second DMA transfer is ended. In the first stream storing means 702, therefore, an overflow occurs in the first stream from the stream inputting means.
Similarly, in the case where, when the processing unit 704 requests the second DMA transfer after the processing unit requests the first DMA transfer, the data amount is not sufficient for starting the transfer to the first stream storing means 702, the bus master device must wait to perform the second DMA transfer until the first DMA transfer is ended. Therefore, an underflow occurs in the second stream storing means 706.